Drum memory protect arrangement

ABSTRACT

A drum memory system is described including the circuits and their system oriented relationship necessary to reduce the probability of destroying the data stored on a rotating magnetic drum due to common faults within the memory logic and linear write-read system. The problems associated with power supply failures, the most common faults, are treated.

United States Patent 1191 Belcastro 1 Nov. 12, 1974 DRUM MEMORY PROTECT 3,261,980 7/1966 McCartney ct 111 some ARRANGEMENT 3.339.081 8/1967 Borden ct a1. 307/86 3.483,. 41 12/1969 Wright 1. 340/1741 B Inventor: Richard J. Belcastro, Schaumburg, 3.518.986 7 1970 Woods et 111 .1 307/86 111. 3,535,560 10/1970 Cliff 340/1715 7 [73] Assigneez GTE Automatic Electric 3,551,746 l../l970 Rubner 3(17/87 Laboratories Incorporated, Northlake, m Przmary E.ranuner-Ga rcth D. Shaw Assistant E.\'aminerM1chac1 Sachs [22] F1led: Apr. 6 1973 [21] Appl. No.: 348,542 57 ABSTRACT A drum memory system is described including the cir- U-S. Cl. uit and their ystcn riented rclationghip necessary [5 Cl. to reduce the probability f destroying thc dulu tored 1 Field-0f Search 34O/l74-1 B, 174-1 172-5; on a rotating magnetic drum due to common laults 307/85, 86, 87; 1 79, 103 within the memory logic and linear write-read system. The problems associated with power supply'failurcs. 1 kefel'encifs Clted the most common faults, are treated. UNITED STATESPATENTS 5 Cl 36 D 3,172,091 3/1965 Friend 340/l74.l aims rawmg gums SYSTEM SHOW/N6 MEMORY PROTECT C/FiCU/T 8 THE MEMORY PROTEC T/ON INTERFACE BTYIEM BIT 0 SEGMENT SELECT HEAD SEGMENT 5 SEL 561' i i 7 3 amcu/r (H50) SEGMENT N g g .,MEMORY g i 5ZZ PRor1-r 24vca/m a, w P5T0 74%) msssr 1 SE6 Ema: HS FLT V24 I OUT 7 0s 0 N wmrs READ AMPLIFIERS MP6 wmrz H L l-s ro "|"Tn RITE AC6 CKZfRR a it 5A0 RESET, RESET CONTROL 5 (w RC) SYST ERR wmrz m Psm 0N PWR SUPPLY V D CONTROL v-s +5 V+5 +24 v24 SEQUENCE -p- V (P30) 24c BAR PATENIU, HJV 1 2 [974 SHEET 02 0F 24 FIG. 2 oRuIv DATA, DAR READBACK & IIvAIcAmR BITS J 5 0 0A a BLOCK DIAGRAM 860 COUNTER ig 2 5, 0R I cTR/DAR ro- I BINARY couAIrIsR DATA FORCED v CAPTURED couur CABLE ERROR 25 0 DRUM ADDRESS ADDRESS REGISTER ADDRESS r0 SEGMEN? A new PAD SEQUENCE CONTROL B50005 *CONTROL cxr.

PA INDICATOR PAD oArA B corvrnoz. CKT.

CONTROL CABLE Am 26 0 CARD 0 DRUM BUFFER REGISTER A FIIIQ I 22355011? 255" To a FROM RECORD/"6 INDICATOR W3 oArA RECORDING cIR UIT g j ckrs. FIG. [9A FRoM PAD saws/v05 corvrRoL 2A 0A0 BLOCK DIAGRAM coIvrRoL cxr FROM ssamewr 050005 CKT. Am RECORDING g g gg g ggg g l:: L L i 26 0 WRITE i A WRITE READ READ l A ooIvrRoL I r0 L rpur MEMORY BUS PROTECT l/I8 CKT cIRcuIr c L0 g I flfigi/ITL gscoRoIru KT. I CLOCK HEAD WRITE I SELECT l w/ 9AM? {CONTROL 5252; LCbfg c/Rcwr l l WRITE AMPS. I I (CTW) L TRANSF I I I I4 1 0 8ERROR I x l BINARY couurm CHEEK I Lil/8 cxr (BC :CLOCK INDICATOR ans 5%" OUTPUT L i :"RP &' DIP CLOCK PULSES PATENTEU 1 3.848.262

SHhU 01 0F 24 DAC PERIPHERAL k ADAPTER REA/J T sf%\fi, READ A TRANS F 0c00E W090 mom 0mm sr 3v SEND I55 PA OUTPUT BU DCU WILL SEND PA SEND START READ EN COUNTER T0 3 E A RC H RECORDING CIRCUITS CONTENTS 0F S'PE CI FIE D CONT, 00$ COUNTER STREAM 0 TRANSFERRED 0m SENT TO TU D89 N0 ENABLE ENABLE M) BINARY BCD QJINCIDENCE CO INCIDENCE YES CHECK CHECK. V

D A DECUDE SELECT 0 0 PA ERROR ERROR OUTPUT BUS 0 cu (A $500.

SEN z c uvrm cow) MODE PARITY r0 ocu ERROR ERROR E 0 PA coursms OF 5520 EN r0 SPEC/F159 'z zm I r0 QAR I SWITCH PA r0 INTERLACED CONTROL SHEET 05 0F 24 FIG 5 I I DAc PERIPHERAL ADAPTER WRITE TRANSFER FL OWCHA RT ROUTE I r0 DAR SWITC H PA T0 INTERL ACED C 0N THOL 08!? ML BE 4 LoADED gigs/551g uNDER DCU C CONTROL ERROR SEGMENT SELECTED sEND I88 T0 DCU A SEGMENT ii? 1Z5 sELEcr V L& To REc0RD ERROR CIRCUITS DCU WILL MODE s ND srARr ERROR couNrER sEARcN CONTENTS OF SPECIFIED COUNTER rRANsEERRED ENABLE To PAR/TY BCD ERROR CO/NCIDENCE END 0F ENABLE CHECK rRANsEER BINARY COINCIDENCE CHECK SEND Z COUNTER T0 DCU PATENTE' HEY I 2 I974 3. 848.252 sum 0B OF 24 FIG. 6 T I K ASSOC/A IVE SEARCH 4 5:25:25 mnrcu c/Rcu/r -|sEARcH REGISTER msx REGISTER 305 .5 7 SEARCH REGISTER 2 BUS A MASK REGISTER 2 r SEARCH REGISTER 3 MASK REGISTER 3 g (cn g 1311s! 52/25 BUFFER nee/m5 f -26 BIT BUS an ASSOC/AT/VE SEARCH CONTROL (241 cap comma/v CONTROL: wrmku BLOCK TRAN3FER (24) f'g r CONTROL colvmoL A DATA (25 (I01 v(I) mm: 1

fi r z vfB/ ADD PAR/TY DATA 4 R BU GENERA r5 ADDRESS INITIALIZATION L D CONTROL (26) ADDRE S 4 Bus 6 our PUT PAR/TY DAM (g /5 GENERATE a aerscr #31: I D noonsss (26 mm (26:) INPUT Prnm d5 DETL'CT L 5 u3" BUS A DA TA SHEET Bus A MID Z COUNTER ULT/PLEX CKT nCOlII/CIDEIVCE 7 IVABLE PULS REGISTER CONTROL WIT/FLEX DC U AND BLOCK TRANS CONTROL FROM ASSOC CKTS i 55213; TO 0131: p g E CROSS U3 CORE BUFFER REG DIRECT D E CODES .DIRECTIVE BUS C PAR/TY PAR/TY C HK BUS C Jeans goons-3s 8 CPD- DLI IAR COUNT FRI *DCPZ INITIAL- ZA TI ON DIRECTIVES -,iCONTROL FIG. 8A ECU MODE CONTROL common SET 8 RST ENABLE I FROM ASSOC) EN CHI? CAR CONTROL MCLEAR(A LL CKTSI +-WORKING WITH E4 MLA$ s50 sLAs s50 :wcu IDLE (SENSE) RLAD " IIAR [.1 ZEflrr T IWNTMDDRESS FOR UNIT TABLE) CPD+ 23 sgfif imcu ERR-b mun REV CONTROL DRP COUNT BUS Ag co READ SEO BLOCK MARK ERR TO REG CONTROL MPX cu TIMEOUT (SENSE) CORE WRITE REG RITE VSEQLEIVCE :g aa o 9 REQUEST RITEEMGBLE LATCH WRI TE SET END a 00R -com:- Access .A TIME RBL.($EN5EI I our READ EEQUES END 1 SEQUHYCE .011 ATCH FRI DCPZ T-TO REC CONTROL MPX IAI? COUNT DCU ERRORS ENTER ETs (115500) DAC ERRORS l SEQUENCE -l TO REG CONTROL MPX 1""'*DCU ERROR IINTERRUPTI F' DCU READY (INTERRUPTI l ERR TERM :TO REG CONTROL MPX FRI DCPZ DATA LOA DED-+ DATA A VAIL SHAPE mamar ERROR /$TA TUS in cans (SENSE I was READYISENSEI CLOCK TRACK ERROR (sense) DL =OATA LOADED CP DA=DATA AVAILABLE CP PAIEmg m I 21974 i SHEET 09 [1F 24 DCU READ SEQUENCE v 0N FRI- EN BUS A man as on UN FRI- EN can r0 0 pop 2 EN CAR r0 0 503 ON rm- I$T STEP u? PCP? DL 01v m m Low IMULATE Y "l STEP LR 0L 0P gr p CAR DATA I RESETREAD I l J LOADED m f gm 3,; ON P4 I V COUNTER EVER LAST PRN TRANSFER CHECK JR 2; $51 MP ERROR 085,25: Y INHIBIT READ szousncs m N LR LR 0 NVOLVED DBR 26=I Y LR= 0 I P2 mp DR BLK MK DRB26=I an 26= I L.

L. RESET can I SET a $50 l' gg (PZ- ncPI I LATCH RESET READ Y 53,5? s50 nzssr @5 IT 25 eus A an an N AND ms 08!? AND EN can (P P2v WRITE REQ T0 CAM) CAR To 0 As'sIfiITIVE Tani 552150 LOAD can P2 55am suns ssaumg TERM BUS BU$ s50 A PAR/TY N A PAR/TY L rcH 000 pz-mp N a y Pa r 805 PZ-TCP R 0 PA mry SET Bus CPARITY Y ERR c N 00 I. nzsz'r we IJNI'IIBIT sm. INHIBIT assr wms rmzaur ERR zmrg READ Wm 'slIur SET BY ocu rmzour FORM ,5

PATENIE nuv 1 2:974

sum 1a or 24 FIG. I7

q) i pcu SEQUENCE FLOW mrznnup mu: WAIT WA I r (ocu ISIDLEI l l I 1 CPD CPD CPD CPD SPILL MAINTENANCE CLEAR INITIAL/2E & DUMP ucu & urns IN/T/ALIZE ERROR TE RM/NATION SEQUENCE TERMINATION SEQUENCE VSETERR /smr //v cons ssrvss LINE TE RMINA TION SEQUENCE ERROR INTERRUPT NOTES I. CPD DIRECTIVE= CPD INITIAL/2E CPD CLEAR, CPD SP/LL,CPD MAINTENANCE 2. DCU SEQUENCE SINGLE 8 MULTI LEVIL ASSOC. SEARCH CPD & PILL SEQ.

TERMINATION SEQ.

INI TI LIZA TION SEQ.

BLOCK TRMBFER WRITE SEQ.

BLOCK TRANSFER READ SEQ.

OMS MAINTENANCE SEQ. CPD MAINTENANCE SEQ.

ERROR TERMINATION SEQ.

ERROR INITILIZATION SEQ.

5 THE INTERRUPTIS GENERATED BY CMC E RMINA TION SEQUENCE EXECUTE DMS AINTENANCE FORCE ERRORS) i ocu TIME our E ma REA 0 Y MERRUPT ERROR TE RM I NA TION SEQUENCE TERM/NA TI ON SEQUENCE SENSE LINE MALFUNCT ON NOTE 5 YES 60 INACTIVE NOT READ) (ALSO NOT IDLE,

YES

GO INACTIVE NOT READY {ALSO NOTIDLE SENSE LINE DCU TIME OUT ERQOR INT RRUPT ACCE S S TRBL 

1. In a rotating memory system having a rotating memory and having write and read head means, first power means for driving the rotating memory, second power means for powering the head means, third power means for inhibiting the write and read means and fourth power means for enabling said write and read head means, a memory protect circuit means operated upon application of said first power means to thereafter enable said second and third power means said memory protect circuit means further including power level monitor means operated to provide an output upon any one of said power means going out of range to first disable said fourth power means, and monitor means for sensing the speed of said rotating memory and for providing an output corresponding to said speed to enable said fourth power means so that said fourth power means enables said write and read head means in response to said monitoring means sensing certain rotating memory speeds.
 2. In a rotating memory system as claimed in claim 1 wherein said rotating memory is a magnetic drum having a plurality of write and read heads associated therewith, a corresponding plurality of amplifiers and head select circuit means, wherein said third power means is for said head select means.
 3. In a rotating memory system as claimed in claim 2 wherein said memory system includes at least a first and a second ''''fourth'''' power means and where said memory protect circuit means includes means connected to each said first and second ''''fourth'''' power means for receive power.
 4. In a rotating memory system as claimed in claim 3 wherein said power level monitor means includes a crowbar circuit to disable said fourth power means.
 5. In a rotating memory system as claimed in claim 4 wherein said memory protect circuit means includes a means to provide a reset signal to said write and read head control means prior to all power means being enabled. 